Xilinx CPLDs


Latest News:
4-04-2014:
Added Logic Analyzer 2 project which uses XC9572XL CPLDs to control sampling and 24 input channels into SRAM.

Development Tools:
All Projects:

 Counter Display
 Logic Analyzer 2


Counter Display:
Xilinx Project Navigator files: Lcd.zip (just the source Lcd.v ) This is about 2004 vintage code.
Device: Coolrunner 2 CPLD
This project uses a surplus LCD that I got in the late1970s to display a 4 digit counter.  The development board comes with just one push button and one LED but provides a large area to add your own toys (the other LED indicates power). 
Logic Analyzer 2:

       Picture

Click on images above for larger versions.

Devices: XC9572XL PIC18F2620
Xilinx Project: LA2.zip LA2part2.zip (just the source LA2.v LA2Part2.v) (Version 3-05-2014)
PIC Project: CBLib CBLA2 (CBLA2.c) (Version 1.7 3-11-2014) For other PIC projects see here.
Schematic: L2A.pdf (Version 0.9 3-31-2014)
Simulation: LA2SimPack.zip (3-05-2014) For simulator, waveform viewing tools and netlist creator see here.
PC Side Code: LogicAnalyzer2.zip
(Version 0.04 3-26-2014)
Other Logic Analyzers: Very old   Very simple and cheap
This project uses a couple XC9572XL 5V tolerant CPLDs, some static RAM, a PIC microcontroller and some glue logic to form a 24 channel 32K deep 30ns per sample logic analyzer.  The sampling rate can be varied from 30ns to 250us and can also be controlled by an external clock with selectable delays and dividers.  The machine also has 3 primitive 0 to 5 volt meters and has a 5V TTL compatible programmable clock generator which can go from 100 Hz to 2.5 MHz.

A trigger condition can be specified using each of the 24 inputs to determine when to start taking samples.  The number of channels (8,16 or 24) and number of samples (4K, 8K, 16K or 32K) can be controlled through the GUI.  The less samples and channels used the faster the update rate.  There is also a window mode where only the samples being displayed are uploaded from the machine.  This improves the update rate at the expense of not being able to see data before or after the time displayed in the current display window.

The PIC microcontroller communicates with the host via an FTDI USB to serial TTL cable.  The PIC controls the two CPLDs using SPI hardware in the PIC plus SPI logic programmed into the CPLDs.  This serial interface runs at 10 MHz when the CPLDs are clocked with the 30ns clock cycle (33.33MHz).  The PIC writes the trigger patterns into the CPLDs and controls the sampling process.  Once the samples are captured, the PIC uses the CPLDs to read data from the RAM and send the results back over the SPI interface and then up to the host over the FTDI cable.


The project was developed using Verilog to describe the CPLDs as well as Verilog to simulate the design with the address generators and RAM to verify the schematic before building and also to verify the design would work.  All the files used to simulate the project are included in the LA2SimPack.zip file above.  There is also a link to free tools to run the simulations and view the results.


The schematic was captured using CadSoft's free Eagle tool.  I wrote a little program to convert the pinlist and parts exported from the tool into a Verilog language netlist.  I also created models for the various TTL parts that I used to allow me to create a full board simulation of the system before getting out my soldering iron.  Underneath the board is point-to-point wiring using nice thin wire-wrap wire.  Creating a good simulation environment for a project takes a good amount of time up front but it pays off in the end.




Last Updated April 4th, 2014
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